Thin Film Transistor Package
The thin film transistor package combines a novel dielectric ink developed at the XRCC, with a high purity, single-walled carbon nanotube ink developed by NanoIntegris. The materials package improves the overall performance of printed high-mobility p-type transistors..
Printing transistors, the next frontier in wearable and flexible electronics, offers manufacturers a low-cost way to add intelligence or computing power to a wide range of surfaces, such as plastic or fabric. Printable semiconducting and dielectric materials enable flexible tags, sensors and displays. Compatibility between semiconducting and dielectric materials is critical for reliable processing and device performance.
One of the challenges that has limited the implementation of single-walled, carbon nanotube-based thin film transistors is that they exhibit considerable hysteresis. The thin film transistor package overcomes this issue by using Xerox ink as a dielectric and encapsulant, ensuring compatibility between semiconducting and dielectric materials, and enabling reliable processing and device performance. The article, “Hysteresis free carbon nanotube thin film transistors comprising hydrophobic dielectrics” in the Journal of Applied Physics Letters discloses how this new materials package addresses these performance issues
“XRCC and NanoIntegris are providing a materials package that enables fabrication of highly functional printed electronic components,” said Brynn Dooley, manager of XRCC’s Electronic Materials Business. “This new materials solution will help our clients with their innovation mandates.”
(Click HERE for the official Xerox Press Release announcing this parternship)
Download: Technical Specifications Sheet
The IsoSol-S100 product has been a featured material within numerous research efforts. The primary usage for the IsoSol-S100 material is for the creation of thin film transistors. What makes this material extremely appealing is that its usage enables the creation of thin film transistors that are fully printed, high-performing, flexible, stable, scalable, and low cost, with the capacity to span large areas. The addition of the dielectric promotes device stability and minimizes hysteresis.
TFT/ Logic Circuit Building Blocks 
NanoIntegris’ IsoSol-S100 material was ink-jet printed at 93 mg/L onto silicon test chips using <20µm drop spacing. The transistors had dense uniform network spanning the source and drain with an average hole mobilities of ~30 cm2/Vs, and on-state current densities greater than 0.75 mA/mm, with on/off ratios of 106. Transistors were generated on flexible polyethylene terephthalate (PET) substrate with silver gate electrodes and high-k BaTiO3 dilelectric layers, printed via a R2R gravure printing process. The IsoSol-S100 was inkjet printed at 50 mg/L along with silver source/ drain contacts, defining a channel of 1000 µm x 150 µm. The on/off ratios were determined to be 7x104 with a subthreshold swing of 1.8V/decade, a transconductance of 0.26 µS/V, a threshold voltage of -2.5V, a calculated capacitance of 6.5 nF/cm2, and a mobility of 6cm2/Vs. When the the XDI-DCS dielectric is printed as a layer atop the TFT, stability is increased, as transfer curves remain unchanged for months, and the encapsulated device exhibits minimal hysteresis (<0.2V) for voltage sweeps of ± 10V. Such encapsulated TFTs were utilized to create an inverter that maintained a constant level of output digital signal during a continuous operation time of 140 minutes and was intended to be used as building blocks for logic circuits.  ACS Appl. Mater. Interfaces 2016, 8, 27900-27910.
Hysteresis-Free CNT-TFTs for Emerging Electronic Devices 
Top-gated CNT Thin Film Transistors (TFTs) were generated on 25 µm thick Kapton films using NanoIntegris’ IsoSol-S100 material as the active channel, silver nanoparticle ink as the electrode, and the XDI-DCS as the hydrophobic gate dielectric.
All layers of the TFT were printed using an aerosol jet printer with typical channel lengths of 120µm and width of 200µm, exhibiting unipolar, p-channel operation with negligible hysteresis (~0.23V) between forward and reverse sweeps in gate-source voltage. The width-normalized ON-current of the device was calculated as 6.65µA/mm at Vds = -2.0V and Vgs = -40V with an ION/IOFF of 6×104. A Peak transconductance of 4.62×108 S and a device mobility of 16.1 cm2/Vs were also achieved.
With alternatively applying a positive or negative bias at the back-gate, the threshold voltage and hysteresis of the fully printed CNT-TFTs can be tuned on demand which may be explored potentially as stable memory devices at room temperature. The TFTs also exhibited negligible variations in transfer characteristics down to a curvature radius of 1mm even after 1000 cycles, without cracking or delamination. Such TFTs pave the way toward all-layer printed, flexible, and low-cost CNT-TFTs for practical applications in emerging electronics such as wearable, foldable, and biointegrated devices.
 Adv Electron. Mater. 2017, 1700057
We currently offer this product in two forms:
1. A stand-alone dielectric ink/ paste.
2. A discounted package including our IsoSol-S100 solution with an appropriate mass of dielectric.
Gram and multi-gram price quotes available by request. Additional discounts also available for large volume orders.
For more information contact our Sales Manager at firstname.lastname@example.org or call +1-866-650-0482.
|10g XDI-DCS Dielectric Ink||$160.00|
|1mg IsoSol-S100 Solution||$700.00|
|1mg IsoSol-S100 Solution + 10g XDI-DCS Dielectric Ink||$775.00|