Completely Printed, Flexible, Stable, and Hysteresis-Free Carbon Nanotube Thin-Film Transistors via Aerosol Jet Printing

Application: Transistors

Citation: Changyong Cao, Joseph B. Andrews, Aaron D. Franklin,Adv. Electron. Mat.. (2015), 10 April 2017.

Summary: Nanomaterials offer an attractive solution to the challenges faced for low-cost printed electronics, with applications ranging from additively manufactured sensors to wearables. This study reports hysteresis-free carbon nanotube thin-film transistor (CNT-TFTs) fabricated entirely using an aerosol jet printing technique; this includes the printing of all layers: semiconducting CNTs, metallic electrodes, and insulating gate dielectrics. It is shown that, under appropriate printing conditions, the gate dielectric ink can be reliably printed and yield negligible hysteresis and low threshold voltage in CNT-TFTs. Flexible CNT-TFTs on Kapton film demonstrate minimal variations in performance for over 1000 cycles of aggressive bending tests. New insights are also gained concerning the role of charge trapping in Si substrate-supported devices, where exposure to high substrate fields results in irreversible degradation. This work is a critical step forward as it enables a completely additive, maskless method to fully print CNT-TFTs of direct relevance for the burgeoning areas of flexible/foldable, wearable, and biointegrated electronics.

Improving contact interfaces in fully printed carbon nanotube thin-film transistors

Application: Transistors

Citation: C Cao, JB Andrews, A Kumar, AD Franklin,ACS nano (2015), 10.5 (2016): 5221-5229.

Summary: Single-walled carbon nanotubes (CNTs) printed into thin films have been shown to yield high mobility, thermal conductivity, mechanical flexibility, and chemical stability as semiconducting channels in field-effect, thin-film transistors (TFTs). Printed CNT-TFTs of many varieties have been studied; however, there has been limited effort toward improving overall CNT-TFT performance. In
particular, contact resistance plays a dominant role in determining the performance and degree of variability in the TFTs, especially in fully printed devices where the contacts and channel are both printed. In this work, we have systematically investigated the contact resistance and overall performance of fully printed CNT-TFTs employing three different printed contact materials. Ag nanoparticles, Au nanoparticles, and metallic CNTseach in the following distinct contact geometries: top, bottom, and double. The active channel for each device was printed from the dispersion of highpurity (>99%) semiconducting CNTs, and all printing was carried out using an aerosol jet printer. Hundreds of devices with different channel lengths (from 20 to 500 μm) were fabricated for extracting contact resistance and determining related contact effects. Printed bottom contacts are shown to be advantageous compared to the more common top contacts, regardless of contact material. Further, compared to single (top or bottom) contacts, double contacts offer a significant decrease (>35%) in contact resistance for all types of contact materials, with the metallic CNTs yielding the best overall performance. These findings underscore the impact of printed contact materials and structures when interfacing with CNT thin films, providing key guidance for the further development of printed nanomaterial electronics.

Fully Printed Foldable Integrated Logic Gates with Tunable Performance Using Semiconducting Carbon Nanotubes

Application: Transistors

Citation: Le Cai, Suoming Zhang, Jinshui Miao, Zhibin YuChuan Wang,Adv. Functi. Mat.. (2015), Volume 25, Issue 35, pages 5698–5705.

Summary: The realization of large-area and low-cost flexible macroelectronics relies on both the advancements in materials science and the innovations in manufacturing techniques. In this study, extremely bendable and foldable carbon nanotube thin film transistors and integrated logic gates are fabricated on a piece of ultrathin polyimide substrate through an ink-jet-like printing process. The adoption of a hybrid gate dielectric layer consisting of barium titanate nanoparticles and poly(methyl methacrylate) has led to not only excellent gating effect but also superior mechanical compliance. The device characteristics show negligible amount of change after up to 1000 cycles of bending tests with curvature radii down to 1 mm, as well as very aggressive folding tests. Additionally, the electrical characteristics of each integrated logic gate can be tuned and optimized individually by using different numbers of carbon nanotube printing passes for different devices, manifesting the unique adaptability of ink-jet printing as a digital, additive, and maskless method. This report on fully printed and foldable integrated logic gates represents an inspiring advancement toward the practical applications of carbon nanotubes for high-performance and low-cost ubiquitous flexible electronics.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Application: Transistors

Citation: Martin Held, Stefan P. Schieß, Dominik Miehler, Florentina Gannott, Jana Zaumseil,Appl. Phys. Lett.. (2015), 107, 083301.

Summary: Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

High-frequency performance of scaled carbon nanotube array field-effect transistors

Application: Transistors

Citation: Ralph Krupke , Mathias Steiner , Michael Engel , Yu-Ming Lin , Yanging Wu , Keith Jenkins , Damon Farmer , Jefford Humes , Nathan Yoder , Jung-Woo Seo , Alexander Green , Mark Hersam , Phaedon Avouris, Nature Nanotechnology (2013), 101, 053123 (2012).

Summary: We report the radio-frequency performance of carbon nanotube array transistors that have been realized through the aligned assembly of highly separated, semiconducting carbon nanotubes on a fully scalable device platform. At a gate length of 100 nm, we observe output current saturation and obtain as-measured, extrinsic current gain and power gain cut-off frequencies, respectively, of 7 GHz and 15GHz. While the extrinsic current gain is comparable to the state-of-the-art, the extrinsic power gain is improved. The de-embedded, intrinsic current gain and power gain cut-off frequencies of 153 GHz and 30 GHz are the highest values experimentally achieved to date. We analyze the consistency of DC and AC performance parameters and discuss the requirements for future applications of carbon nanotube array transistors in high-frequency electronics.

Enrichment of large-diameter semiconducting SWCNTs by polyfluorene extraction for high network density thin film transistors

Application: Transistors

Citation: Jianfu Ding, Zhao Li, Jacques Lefebvre, Fuyong Cheng, Girjesh Dubey, Shan Zou, Paul Finnie, Amy Hrdina, Ludmila Scoles, Gregory P. Lopinski, Christopher T. Kingston, Benoit Simard, and Patrick R. L. MalenfantNanoscale Issue 4, 14 Jan 2014.

Summary: A systematic study on the use of 9,9-dialkylfluorene homopolymers (PFs) for large-diameter semiconducting (sc-) single-walled carbon nanotube (SWCNT) enrichment is the focus of this report. The enrichment is based on a simple three-step extraction process: (1) dispersion of as-produced SWCNTs in a PF solution; (2) centrifugation at a low speed to separate the enriched sc-tubes; (3) filtration to collect the enriched sc-SWCNTs and remove excess polymer. The effect of the extraction conditions on the purity and yield including molecular weight and alkyl side-chain length of the polymers, SWCNT concentration, and polymer/SWCNT ratio have been examined. It was observed that PFs with alkyl chain lengths of C10, C12, C14, and C18, all have an excellent capability to enrich laser-ablation sc-SWCNTs when their molecular weight is larger than 10 000 Da. More detailed studies were therefore carried out with the C12 polymer, poly(9,9-di-n-dodecylfluorene), PFDD. It was found that a high polymer/SWCNT ratio leads to an enhanced yield but a reduced sc-purity. A ratio of 0.5–1.0 gives an excellent sc-purity and a yield of 5–10% in a single extraction as assessed by UV-vis-NIR absorption spectra. The yield can also be promoted by multiple extractions while maintaining high sc-purity. Mechanistic experiments involving time-lapse dispersion studies reveal that m-SWCNTs have a lower propensity to be dispersed, yielding a sc-SWCNT enriched material in the supernatant. Dispersion stability studies with partially enriched sc-SWCNT material further reveal that m-SWCNTs : PFDD complexes will re-aggregate faster than sc-SWCNTs : PFDD complexes, providing further sc-SWCNT enrichment. This result confirms that the enrichment was due to the much tighter bundles in raw materials and the more rapid bundling in dispersion of the m-SWCNTs. The sc-purity is also confirmed by Raman spectroscopy and photoluminescence excitation (PLE) mapping. The latter shows that the enriched sc-SWCNT sample has a narrow chirality and diameter distribution dominated by the (10,9) species with d= 1.29 nm. The enriched sc-SWCNTs allow a simple drop-casting method to form a dense nanotube network on SiO2/Si substrates, leading to thin film transistors (TFTs) with an average mobility of 27 cm2 V−1 s−1 and an average on/off current ratio of 1.8 × 106 when considering all 25 devices having 25 μm channel length prepared on a single chip. The results presented herein demonstrate how an easily scalable technique provides large-diameter sc-SWCNTs with high purity, further enabling the best TFT performance reported to date for conjugated polymer enriched sc-SWCNTs.

All-printed and transparent single walled carbon nanotube thin film transistor devices

Application: Transistors

Citation: Sajed, Farzam ;Rutherglen, Christopher;Applied Physics Letters Sep 2013, 103, 14,143303 – 143303-4.

Summary: We present fully transparent single-walled all-carbon nanotube thin film transistors (SWCNT TFT) fabricated using low-cost inkjet printing methods. Such a demonstration provides a platform towards low cost fully printed transparent electronics. The SWCNT TFTs were printed with metallic and semiconducting SWCNT using a room temperature printing process, without the requirement of expensive cleanroom facilities. The unoptimized SWCNT TFTs fabricated exhibited an Ion/off ratio of 92 and mobility of 2.27 cm2V-1s-1 and transmissivity of 82%. The combination of both high electrical performance and high transparency make all-SWCNT TFTs desirable for next generation transparent display backplanes and products such as Google Glass.

Fully Printed, High Performance Carbon Nanotube Thin-Film Transistors on Flexible Substrates

Application: Transistors

Citation: Pak Heng Lau, Kuniharu Takei, Chuan Wang, Yeonkyeong Ju , Junseok Kim , Zhibin Yu, Toshitake Takahashi, Gyoujin Cho, and Ali Javey;Nano Lett. 2013, 13 (8), pp 3864–3869.

Summary: Fully printed transistors are a key component of ubiquitous flexible electronics. In this work, the advantages of an inverse gravure printing technique and the solution processing of semiconductor-enriched single-walled carbon nanotubes (SWNTs) are combined to fabricate fully printed thin-film transistors on mechanically flexible substrates. The fully printed transistors are configured in a top-gate device geometry and utilize silver metal electrodes and an inorganic/organic high-κ (17) gate dielectric. The devices exhibit excellent performance for a fully printed process, with mobility and on/off current ratio of up to 9 cm2/(V s) and 105, respectively. Extreme bendability is observed, without measurable change in the electrical performance down to a small radius of curvature of 1 mm. Given the high performance of the transistors, our high-throughput printing process serves as an enabling nanomanufacturing scheme for a wide range of large-area electronic applications based on carbon nanotube networks.

Short-Channel Transistors Constructed with Solution-Processed Carbon Nanotubes

Application: Transistors

Citation: Sung-Jin Choi, Patrick Bennett, Kuniharu Takei, Chuan Wang, Cheuk Chi Lo, Ali Javey, and Jeffrey Bokor, ACSNano 2013, 7 (1), pp. 798-803.

Summary: We develop short-channel transistors using solution-processed single-walled carbon nanotubes (SWNTs) to evaluate the feasibility of those SWNTs for high-performance applications. Our results show that even though the intrinsic field-effect mobility is lower than the mobility of CVD nanotubes, the electrical contact between the nanotube and metal electrodes is not significantly affected. It is this contact resistance which often limits the performance of ultrascaled transistors. Moreover, we found that the contact resistance is lowered by the introduction of oxygen treatment. Therefore, high-performance solution-processed nanotube transistors with a 15 nm channel length were obtained by combining a top-gate structure and gate insulators made of a high-dielectric-constant ZrO2 film. The combination of these elements yields a performance comparable to that obtained with CVD nanotube transistors, which indicates the potential for using solution-processed SWNTs for future aggressively scaled transistor technology.

Comparative study of solution-processed carbon nanotube network transistors

Application: Transistors

Citation: Sung-Jin Choi, Patrick Bennett, Kuniharu Takei, Chuan Wang, Cheuk Chi Lo, Ali Javey, and Jeffrey Bokor, AIP Applied Physics Letters 2012, 101, 112104.

Summary: Carbon nanotube networks in thin-film type transistors were studied experimentally, comparing the use of pre-separated semiconducting enriched nanotubes (90% and 99% purity) to examine how topology affects the properties of the devices. Measurements are reported for two deposition methods used for network formation: random and spin-aligned deposition methods. The results show that the thin-film transistors fabricated via spin-aligned deposition demonstrate better electrical uniformity and performance than those produced by the random network deposition method. Our results imply that coverage and alignment are strongly correlated with the properties of the devices and should therefore be simultaneously optimized for improved electrical uniformity and performance.

Extremely Bendable, High-Performance Integrated Circuits Using Semiconducting Carbon Nanotube Networks for Digital, Analog, and Radio-Frequency Applications

Application: Transistors

Citation: Chuan Wang †‡§, Jun-Chau Chien †, Kuniharu Takei †‡§, Toshitake Takahashi †‡§, Junghyo Nah †‡§, Ali M. Niknejad †, and Ali Javey *†‡§, ACS Nano Letters, 2012, 12 (3), pp. 1527-1533.

Summary: Solution-processed thin-films of semiconducting carbon nanotubes as the channel material for flexible electronics simultaneously offers high performance, low cost, and ambient stability, which significantly outruns the organic semiconductor materials. In this work, we report the use of semiconductor-enriched carbon nanotubes for high-performance integrated circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The as-obtained thin-film transistors (TFTs) exhibit highly uniform device performance with on-current and transconductance up to 15 μA/μm and 4 μS/μm. By performing capacitance–voltage measurements, the gate capacitance of the nanotube TFT is precisely extracted and the corresponding peak effective device mobility is evaluated to be around 50 cm2V–1s–1. Using such devices, digital logic gates including inverters, NAND, and NOR gates with superior bending stability have been demonstrated. Moreover, radio frequency measurements show that cutoff frequency of 170 MHz can be achieved in devices with a relatively long channel length of 4 μm, which is sufficient for certain wireless communication applications. This proof-of-concept demonstration indicates that our platform can serve as a foundation for scalable, low-cost, high-performance flexible electronics.

Fabricating Devices with Dielectrophoretically Assembled, Suspended Single Walled Carbon Nanotubes for Improved Nanoelectronic Device Characterization

Application: Transistors

Citation: Simone Schuerlea, Manish K. Tiwarib, Kaiyu Shoua, Dimos Poulikakosb and Bradley J. Nelson, Microelectronic Engineering (2011), Article in Press.

Integrating carbon nanotubes (CNTs) and nanowires into devices for sensing, actuation and other nanoelectronic applications has the potential to increase device efficiency and lower power consumption. Examples include ultra-high frequency CNT filters and resonators for high sensitivity gas/mass detection. Reliable operation requires careful mechanical and electrical characterization of the integrated CNTs and their contact with electrodes. In this work, we demonstrate a fabrication strategy and integration of suspended single walled CNTs (SWCNTs) on a chip for investigation of the metal nanotube interfacial adhesion strength. A multi-step etching process is used to prepare SWCNTs integrated on TEM compatible chips. Alternating current (AC) dielectrophoresis (DEP) is used for selective SWCNT integration simultaneously overcoming localization issues. The suspended tubes are conducive to mechanical manipulation or electrostatic actuation. In addition, our approach provides fully suspended electrodes for TEM analysis with reduced charging issues that are typically caused by supporting insulating layers. This enables the visualization of failure modes of the tube/electrode contact that have not been previously observed.

Radio Frequency and Linearity Performance of Transistors Using High-Purity Semiconducting Carbon Nanotubes

Application: Transistors

Citation: Chuan Wang, Alexander Badmaev, Alborz Jooyaie, Mingqiang Bao, Kang L. Wang, Kosmas Galatsis and Chongwu Zhou, ACS Nano (2011), 5, 5, 4169–4176.

Summary: This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (ft) of 5 GHz and with maximum oscillation frequency (fmax) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.

High-performance Local Back Gate Thin-Film Field-Effect Transistors Using Sorted Carbon Nanotubes on an Amino-Silane Treated Hafnium Oxide Surface

Application: Transistors

Citation: K C Narasimhamurthy and Roy Paily, Semiconductor Science and Technology (2011), 26, 075002.

Summary: Wafer-scale fabrication and characterization of local back gate semiconducting nanotube thin-film transistors (SN-TFTs) are reported in this paper. The local back gate voltage of the corresponding SN-TFT controls the individual transistor switching. In order to achieve high performance, a high-k dielectric material is employed as a gate oxide and this helped to achieve low-voltage operations, much steeper sub-threshold voltage swings and higher transconductance values. A simple procedure to deposit a high-density single-walled carbon nanotube thin film on an amino-silane-treated hafnium oxide (HfOX) surface is suggested such that a good density of nanotubes is realized without degrading the device on–off current ratio and mobility values. The density of the nanotubes achieved on the silanized HfOX surface is about 40–45 nanotubes µm−2. SN-TFTs exhibit an excellent p-type output characteristic with distinct linear and saturation regions. Local back gate SN-TFTs exhibit an on–off current ratio exceeding 104 and a steep sub-threshold slope of 400 mV/decade. SN-TFTs achieve a maximum current density of 13 μA µm−1, an average threshold voltage of −0.5 V, a maximum normalized transconductance of 18.5 μS µm−1 and exhibit a maximum carrier mobility of 60.6 cm2(Vs)−1.

Air-Stable Conversion of Separated Carbon Nanotube Thin-Film Transistors from p-Type to n-Type Using Atomic Layer Deposition of High-κ Oxide and Its Application in CMOS Logic Circuits

Application: Transistors

Citation: Jialu Zhang, Chuan Wang, Yue Fu, Yuchi Che, and Chongwu Zhou, ACS Nano (2011), 5, 4, 3284–3292.

Summary: Due to extraordinary electrical properties, preseparated, high purity semiconducting carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications. One of the main challenges it still faces is the fabrication of air-stable n-type nanotube TFTs with industry-compatible techniques. Here in this paper, we report a novel and highly reliable method of converting the as-made p-type TFTs using preseparated semiconducting nanotubes into air-stable n-type transistors by adding a high-κ oxide passivation layer using atomic layer deposition (ALD). The n-type devices exhibit symmetric electrical performance compared with the p-type devices in terms of on-current, on/off ratio, and device mobility. Various factors affecting the conversion process, including ALD temperature, metal contact material, and channel length, have also been systematically studied by a series of designed experiments. A complementary metal−oxide−semiconductor (CMOS) inverter with rail-to-rail output, symmetric input/output behavior, and large noise margin has been further demonstrated. The excellent performance gives us the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.

Scalable Complementary Logic Gates with Chemically Doped Semiconducting Carbon Nanotube Transistors

Application: Transistors

Citation: Si Young Lee, Sang Won Lee, Soo Min Kim, Woo Jong Yu, Young Woo Jo, Young Hee Lee, ACS Nano (2011), 5, 3, 2369–2375.

Summary: Use of random network carbon nanotube (CNT) transistors and their applications to complementary logic gates have been limited by several factors such as control of CNT density, existence of metallic CNTs producing a poor yield of devices, absence of stable n-dopant and control of precise position of the dopant, and absence of a scalable and cost-effective fabrication process. Here, we report a scalable and cost-effective fabrication of complementary logic gates by precisely positioning an air-stable n-type dopant, viologen, by inkjet printing on a separated semiconducting CNTs network. The obtained CNT transistors showed a high yield of nearly 100% with an on/off ratio of greater than 103 in an optimized channel length (9 μm). The n-doped semiconducting carbon nanotube transistors showed a nearly symmetric behavior in the on/off current and threshold voltage with p-type transistors. CMOS inverter, NAND, and NOR logic gates were integrated on a HfO2/Si substrate using the n/p transistor arrays. The gain of inverter is extraordinarily high, which is around 45, and NAND and NOR logic gates revealed excellent output on and off voltages. These series of whole processes were conducted under ambient conditions, which can be used for large-area and flexible thin film technology.

Effect of Source, Surfactant, and Deposition Process on Electronic Properties of Nanotube Arrays

Application: Transistors

Citation: Dheeraj Jain, Nima Rouhi, Christopher Rutherglen, Crystal G. Densmore, Stephen K. Doorn, Peter J. Burke, Journal of Nanomaterials (2011), 10.1155/2011/174268.

Summary: The electronic properties of arrays of carbon nanotubes from several different sources differing in the manufacturing process used with a variety of average properties such as length, diameter, and chirality are studied. We used several common surfactants to disperse each of these nanotubes and then deposited them on Si wafers from their aqueous solutions using dielectrophoresis. Transport measurements were performed to compare and determine the effect of different surfactants, deposition processes, and synthesis processes on nanotubes synthesized using CVD, CoMoCAT, laser ablation, and HiPCO.

Radiation Effects in Single-Walled Carbon Nanotube Thin-Film-Transistors

Application: Transistors

Citation: C.D. Cress, J.J. McMorrow, J.T. Robinson, A.L. Friedman, B.J. Landi, Nuclear Science, IEEE Transactions (2010), 57, 6, 3040 – 3045.

Summary: The fabrication, characterization, and radiation response of single-walled carbon nanotube (SWCNT) thin-film field effect transistors (SWCNT-TFTs) has been performed. SWCNT-TFTs were fabricated on SiO2-Si substrates from 98% pure semiconducting SWCNTs separated by density gradient ultracentrifugation. Optical and Raman characterization, in concert with measured drain current Ion/Ioff ratios, up to 104, confirmed the high enrichment of semiconducting-SWCNTs. Total ionizing dose (TID) effects, up to 10 MRads, were measured in situ for a SWCNT-TFT under static vacuum. The results revealed a lateral translation of the SWCNT-TFT transfer characteristics to negative gate bias resulting from hole trapping within the SiO2 and SiO2-SWCNT interface. Additional TID exposure conducted in air on the same device had the opposite effect, shifting the transfer characteristics to higher gate voltage, and increasing the channel conductance. No significant change was observed in the device mobility or the SWCNT Raman spectra following a TID exposure of 10 Mrad(Si), indicating extrinsic factors dominate the transfer characteristics in the SWCNT-TFT devices during irradiation. The extrinsic effects of charge trapping and the role that gas adsorption plays in the radiation response are discussed.

The Polarized Carbon Nanotube Thin Film LED

Citation: Megumi Kinoshita, Mathias Steiner, Michael Engel, Joshua P. Small, Alexander A. Green, Mark C. Hersam, Ralph Krupke, Emilio E. Mendez, Phaedon Avouris, Opt. Express (2010), 18, 25, 25738-25745.

Summary: We demonstrate a light emitting p-i-n diode made of a highly aligned film of separated (99%) semiconducting carbon nanotubes, self- assembled from solution. By using a split gate technique, we create p- and n-doped regions in the nanotube film that are separated by a micron-wide gap. We inject p- and n-type charge carriers into the device channel from opposite contacts and investigate the radiative recombination using optical micro-spectroscopy. We find that the threshold-less light generation efficiency in the intrinsic carbon nanotube film segment can be enhanced by increasing the potential drop across the junction, demonstrating the LED- principle in a carbon nanotube film for the first time. The device emits infrared light that is polarized along the long axes of the carbon nanotubes that form the aligned film.

Macroelectronic Integrated Circuits Using High-Performance Separated Carbon Nanotube Thin-Film Transistors

Application: Transistors

Citation: Chuan Wang, Jialu Zhang, Chongwu Zhou, ACS Nano (2010), 4, 12, 7123–7132.

Summary: Macroelectronic integrated circuits are widely used in applications such as flat panel display and transparent electronics, as well as flexible and stretchable electronics. However, the challenge is to find the channel material that can simultaneously offer low temperature processing, high mobility, transparency, and flexibility. Here in this paper, we report the application of high-performance separated nanotube thin-film transistors for macroelectronic integrated circuits. We have systematically investigated the performance of thin- film transistors using separated nanotubes with 95% and 98% semiconducting nanotubes, and high mobility transistors have been achieved. In addition, we observed that while 95% semiconducting nanotubes are ideal for applications requiring high mobility (up to 67 cm2 V-1 s-1) such as analog and radio frequency applications, 98% semiconducting nanotubes are ideal for applications requiring high on/off ratios (>104 with channel length down to 4µm). Furthermore, integrated logic gates such as inverter, NAND, and NOR have been designed and demonstrated using 98% semiconducting nanotube devices with individual gating, and symmetric input/output behavior is achieved, which is crucial for the cascading of multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.

Fundamental Limits on the Mobility of Nanotube-Based Semiconducting Inks

Application: Transistors

Citation: Nima Rouhi, Dheeraj Jain, Katayoun Zand, Peter John Burke, Advanced Materials (2011), 23, 1, 94-99.

Summary: High mobility and high on/off ratio thin-film transistors are fabricated using solution-based deposition of purified semiconducting carbon nanotubes. A comprehensive spectrum of the density starting from less than 10 tubes μm-2 to the high end of around 100 tubes μm-2 is investigated. This study provides the first important roadmap for the tradeoffs between mobility and on/off ratio in nanotube-based semiconducting inks.

Flexible, Transparent Single-Walled Carbon Nanotube Transistors with Graphene Electrodes

Application: Transistors

Citation: Sukjae Jang, Houk Jang, Youngbin Lee, Daewoo Suh, Seunghyun Baik, Byung Hee Hong, Jong-Hyun Ahn, Nanotechnology (2010), 21 425201.

Summary: This paper reports a mechanically flexible, transparent thin film transistor that uses graphene as a conducting electrode and single-walled carbon nanotubes (SWNTs) as a semiconducting channel. These SWNTs and graphene films were printed on flexible plastic substrates using a printing method. The resulting devices exhibited a mobility of ~ 2 cm2 V -1 s -1, On/Off ratio of ~ 102, transmittance of ~ 81% and excellent mechanical bendability.

Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications

Application: Transistors

Citation: Chuan Wang, Jialu Zhang, Koungmin Ryu, Alexander Badmaev, Lewis Gomez De Arco, Chongwu Zhou, Nano Letters (2009), 9, 12, 4285-4291.

Summary: This paper demonstrates a functioning OLED display device based on a waferscale
assembly of carbon nanotube thinfilm transistors. Using IsoNanotubes S 95%, the University of California produced transistors with high yield (>98%), low sheet resistance (25kΩ/sq), high current density ( 10µA/µm), and superior mobility (52 cm 2 V-1s-1). Moreover, on/off rations of >10^4 were achieved in devices with channel length L>20µm. To the best of our knowledge, these are the best concurrent CNT transistor numbers reported in the literature to date.

80 GHz Field-Effect Transistors Produced Using High Purity Semiconducting Single-Walled Carbon Nanotubes

Application: Transistors

Citation: L. Nougaret, H. Happy, G. Dambrine, V. Derycke, J. -P. Bourgoin, A. A. Green, M. C. Hersam, Applied Physics Letters (2009) 94, 243505.

Summary: In this study, solutions of 99% pure semiconducting nanotubes were used to fabricate SWNT field-effect transistors (FETs) with extrinsic and intrinsic current gain cutoff frequencies of ~15 and ~80 GHz, respectively. Importantly, this study also demonstrates that precise nanotube alignment is not required to achieve excellent performance in high-frequency devices.

Thin Film Nanotube Transistors Based on Self-Assembled, Aligned Semiconducting Carbon Nanotube Arrays

Application: Transistors

Citation: Michael Engel, Joshua P. Small, Mathias Steiner, Marcus Freitag, Alexander A. Green, Mark C. Hersam, Phaedon Avouris, ACS Nano (2008), 2, 12, 2445–2452.

Summary: The IBM T.J. Watson Research Center with Northwestern University fabricated thin-film transistors (TFTs) from DGU produced semiconducting CNTs. To confirm the semiconducting purity of the CNTs, the team synthesized 83 single nanotube transistors from the same DGU produced source material. 82 of the 83 transistors were found to contain a semiconducting nanotube, empirically confirming the material’s calculated level (99%) of semiconducting enrichment.